1. Field of the Invention
The invention relates in general to an analog-digital converter (ADC) and in particular to an ADC employing a multi-thread, parallel processing sigma-delta modulator.
2. Description of Related Art
A sigma-delta ADC is able to digitize an analog signal with relatively high resolution using an inexpensive, relatively low resolution ADC. FIG. 1 is a block diagram illustrating an example prior art sigma-delta ADC for producing a digital output sequence sk representing the time-varying behavior of an analog input signal VIN. ADC 1 includes a sample and hold (S/H) circuit 2 for periodically sampling the VIN signal in response to edges of a clock signal CLK1 to produce a sequence xn of discrete samples of the analog signal. The CLK1 signal frequency is much higher than the analog signal's bandwidth so that VIN is substantially oversampled. A sigma-delta modulator 3 clocked by CLK1 converts the analog sample sequence xn into a digital data sequence yn and a decimator 4 filters and decimates sequence yn to produce the digital output sequence sk.
Within sigma-delta modulator 3, an analog summer 5 offsets xn by the output of a digital-analog converter (DAC) 6 to supply an analog input to a filter 7 having a discrete transfer function H(z) producing an output analog sequence zn. An ADC 8 having very coarse resolution digitizes the zn sequence to produce the modulator's output sequence yn, also providing an input to DAC 6 having the same resolution as ADC 8. Within decimator 4, a digital filter 9 produces an output sequence sn wherein each element is a weighted sum of values of several of the most recent elements of the yn sequence. A down sampler 10 down samples sn to produce elements of output sequence sk at a frequency lower than that of CLK1. Output sequence sk depicts successive amplitudes of VIN with much higher resolution than that of ADC 8. Thus, sigma-delta ADC 1 is able to employ a relatively low resolution ADC 8 to produce relatively high resolution output data sk.
The quantization error of ADC 8 can affect the resolution of ADC 1. FIG. 2 models the quantization error of coarse ADC 8 as an additive noise en within the system wherein the output yn of sigma-delta modulator 3 is a linear combination of the input and the additive noise as follows:       Y    ⁡          (      z      )        =                              H          ⁡                      (            z            )                                    1          +                      H            ⁡                          (              z              )                                          ⁢              X        ⁡                  (          z          )                      +                  1                  1          +                      H            ⁡                          (              z              )                                          ⁢              E        ⁡                  (          z          )                    The transfer function of this modulator seen by input sequence xn is                               G          ⁡                      (            z            )                          =                              Y            ⁡                          (              z              )                                            X            ⁡                          (              z              )                                                                E        ⁡                  (          z          )                    =      0        =                    H        ⁡                  (          z          )                            1        +                  H          ⁡                      (            z            )                                .  The transfer of this modulator seen by the additive noise en is                               F          ⁡                      (            z            )                          =                              Y            ⁡                          (              z              )                                            X            ⁡                          (              z              )                                                                X        ⁡                  (          z          )                    =      0        =            1              1        +                  H          ⁡                      (            z            )                                .  Note that since S/H circuit 2 generates input sequence xn at a sampling rate much higher than the bandwidth of input signal VIN, input sequence xn consists of only relatively low frequency components in this discrete-time system. However, additive noise en is “white noise”, uniformly distributed over the entire frequency range. Choosing H(z) such that F(z) is a high-pass response decreases the noise at low frequencies but increases it at high frequencies. We can also choose H(z) so that input sequence xn sees a feed-through, for example by using a first order loop where       H    ⁡          (      z      )        =                    z                  -          1                            1        -                  z                      -            1                                .  Correspondingly, transfer functions G(z) and F(z) will be.G(z)=z−1, andF(z)=1−z−1.
Thus input sequence xn sees only a delay (z−1), while the additive noise sequence en sees a first order high-pass response (1−z−1). Such a “noise shaping” choice for H(z) reduces the in-band noise, thereby increasing the in-band signal-to-noise ratio. While this choice for H(z) increases the out-of-band noise, digital filter 9 can remove it by employing appropriately adjusted weighting coefficients so that it acts like a low pass filter. Thus, by redistributing quantization error to move most of the additive noise resulting from the ADC's coarse resolution out of the frequency band of the sampled signal, sigma-delta modulator 3 reduces the impact on system resolution of the additive noise produced by its ADC 8.
FIG. 3 depicts a prior art second order sigma-delta ADC 11 including a sample and hold circuit 12 sampling an analog signal VIN at a sampling rate controlled by clock signal CLK1 to produce a sequence of analog samples xn supplied as input to a second-order, single threaded, sigma-delta modulator 13. Modulator 13, clocked by CLK1, produces an output digital sequence yn filtered and decimated by a decimator 14, similar to decimator 4 of FIG. 1, to produce the digital output sequence sk. Modulator 13 includes a summer 15 and a filter 16 for offsetting xn by the output of a DAC 17 and filtering the result to produce an analog sequence wn. A summer 18 offsets wn by the output of DAC 17 and a filter 19 filters the result to produce an analog sequence zn. A low resolution ADC 20 digitizes zn to generate an output digital sequence yn, also supplied as input to DAC 17. The governing recursive formulas for the prior art second-order sigma-delta modulator 13 of FIG. 13 are:zn=zn−1+wn−1−yn−1wn=wn−1+xn−yn
To digitize VIN with high resolution it is necessary either to operate a sigma-delta ADC at a higher sampling frequency or to employ a higher order sigma-delta ADC. Typically, the maximum operating frequency of the components forming aDC's sigma-delta modulator can limit the maximum sampling frequency of the ADC, so it has been necessary to use higher order ADCs to achieve higher resolution. But designers find it difficult to design stable higher order sigma-delta ADCs because the multiple feedback loops are subject to instablity. In practice, the order of filtering rarely exceeds five (5) and is preferably kept under four (4). With the limitation of the order of filtering and limitations imposed by the maximum operating frequency of the components forming a sigma-delta converter, sigma-delta ADCs are rarely used for digitizing signals having a bandwidth higher than a few megahertz. What is needed is sigma-delta converter that can digitize higher bandwidth signals.